Noise shaping control loops are well known in type of analog to digital converters (ADCs) known as sigma-delta (ΣΔ) converters. Such converters are also sometimes called ΣΔ modulators, the modulator term referring to an output digital data stream having a certain symbol pattern, or modulation, imposed upon it by the control loop. The terms ΣΔ modulator and noise shaping control loop are often used interchangeably in the art, although the latter is more descriptive. Circuit designers often like to use such ΣΔ modulators as in many cases they may be simpler to design and cheaper to make than other types of ADCs.
In such a noise shaping control loop, a continuous analog signal is applied at the input, and a digital pattern representative of this signal emerges from the output. The digital signal is created by one or more quantization elements in the control loop, for example, by non-linear elements in the loop such as flip-flops or comparators that have a discrete set of non-continuous output values for any given continuous input quantity.
The “noise shaping” of the control loop relates the loop's ability to manage the deviation from the ideal continuous feedback that the quantization elements necessarily introduce. This deviation from the ideal continuous feedback represents a source of noise in the loop, and it is this noise that is “shaped.” To “shape” the noise means to filter it, generally to make it not appear in certain frequency bands. The loop therefore operates to suppress this noise in certain frequency bands of interest, often at the expense of increased noise in bands that are not relevant to the application.
The band in which the quantization noise is suppressed is determined by the filter in the control loop, i.e., by the frequency dependence of the elements within the control loop. Such a filter design commonly results in the noise being suppressed at low frequencies, for example, in the zero to 20 KHz band as may be required for an audio device. Less common, but of increasing interest in the industry, are so called “band-pass ΣΔ modulators” that have a loop designed to suppress the quantization noise in a specified band. For example, in TV applications it is very desirable to have low noise in the band from 41 MHz to 47 MHz, but not necessary to have low noise at lower (or higher) frequencies. Thus, modulators that have such characteristics are known as “band-pass” modulators since the frequency range of interest is a relatively small band.
FIG. 1 shows a ΣΔ convertor functioning as a simple ADC 100 as is known in the prior art. An input signal is applied to a comparator, or differential circuit, 102, where it is compared to another value, which is the fed-back output of ADC 100. The output of the comparator 102, which is thus the difference between the input and the output of ADC 100, i.e., the “error” in the quantization, is fed to an integrator circuit 104 where it is integrated over time. The result of such integration is fed to a quantizer 106.
Quantizer 106 is clocked by a clock C, and thus will output a value, i.e., “quantize” the input, on each clock pulse. If the clock C is at 1 megahertz (MHz), an output value will be produced every 1 microsecond (μS). If the input to quantizer 106 is greater than 0, the output of quantizer 106 is a value of 1, while if the input to quantizer 106 is less than 0, the output of quantizer 106 is a value of −1. The string of 1 and −1 values is the output of the ADC 100, and is also fed back through a resistor R1 as the other input to comparator 102, to be compared to the input signal.
It is the limitation of the output of the quantizer 106 to only the two values 1 and −1 that is the source of noise in the control loop, as these values will most often be very inexact estimates of the analog input, which may have any value between 1 to −1. For example, a sine wave, which varies continuously between 1 and −1, will be represented solely by a string of values of 1 and −1 in the circuit 100 of FIG. 1.
One of skill in the art will appreciate that an output representing a better estimate of the input would result if the quantizer were able to select from a greater number of values, so that output values closer to the input values from 1 to −1 could be obtained. A set of output values of 1, 0 and −1 would provide an improvement, while a set of output values of 1, 0.5, 0, −0.5 and −1 would provide still further improvement, etc. Thus, designing the quantizer such that a larger set of output possibilities are available increases the mathematical number of information “bits” in the quantizer and reduces the noise in the ADC.
It will also be appreciated that another way of improving the output of such an ADC is to increase the rate at which the input signal is sampled. This requires increasing the speed of operation of the quantizer, and thus the clock speed. However, as will be discussed further below, both increasing the set of output values of the quantizer and increasing its clock speed present other problems that reduce the advantages that ΣΔ modulators may have over other ADCs.
In addition, as will be explained further below, a ΣΔ modulator in which additional integrators and feedback are included (a “second-order” control loop) allows for a maximum signal-to-noise ratio (SNR) at a particular frequency. In some applications, it would be desirable to have multiple such frequencies of low noise.
For these reasons, a simple and inexpensive way of improving the performance of ΣΔ modulators functioning as ADCs may be useful.